This invention relates to an electronic time switch, and more particulaly an electronic time switch capable of electronically interchanging the order of given input information, for example.
The time switch of this type is used to randomly read out data written into a memory device in a predetermined order according to an address designation order based on connection information as in a speech path switch of a digital telephone exchanger. Since a data line connected with a plurality of cells is driven by a memory output, the operating speed of such time switch is lower than those of a register and a logic gate so that such time switch can not be used in a high speed speech path as in the case of an exchange in a wide band or a telephone exchange utilizing a satelite.
Although a time switch utilizing a multiplexer constituted by a shift register and logic gates has been proposed as a time switch not utilizing a memory device, it is constructed to simultaneously select based on a single address information. Where it is desired to construct a large scale time switch, it is essential to use a multi-input OR gate cirucuit which not only decreases the operating speed but also increases the size of the decoder and the number of control lines, thus failing to obtain a practical time switch gate matrix type switch is disclosed in U.S. Pat. No. 4,344,170 in which a plurality of multiplexers of the number equal to that of the data are operated in parallel for the purpose of compensating for the decrease in the operating speed due to the use of the multi-input OR gate circuit. With the system disclosed in this patent, even when the multiplexers operate at a low speed, an exchange speed equal to that of the shift register can be obtained so that a time switch having an extremely high speed can be realized. However, since this system requires a number of hardware components equal to the square of the degree of multiplexing it has been difficult to obtain a large scale system.